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MICRF010
QwikRadio(R) Low-Power UHF Receiver
General Description
The MICRF010 is a single chip, ASK/OOK (ON-OFF Keyed) RF receiver IC recommended for new designs replacing the MICRF007. It provides the same function with sensitivity enhancement, typically 6dB better than the MICRF007. Just like all other members of the QwikRadio(R) family, the MICRF010 achieves low power operation, a very high level of integration, and it is particularly easy to use. All post-detection data filtering is provided on the MICRF010, so no external baseband filters are required. In fact, the entire receiver circuit is made of very few external components and with the 8-pin SOIC package makes it ideal for small printed circuit board area applications. The MICRF010 works in fixed-mode (FIX) operation, which functions as a conventional super-heterodyne receiver. Fixed-mode provides better selectivity and sensitivity performance in comparison with sweep mode used in other Micrel receivers intended for lower cost applications. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com.
QwikRadioTM
Features
* * * * High sensitivity (-104dBm) 300MHz to 440MHz frequency range Data-rate up to 2.0kbps (Manchester encoding) Low power consumption - 2.9mA fully operational (315MHz) - 0.15A in shutdown - 290A in polled mode (10:1 duty-cycle) Shutdown input Automatic tuning, no manual adjustment Very low RF re-radiation at the antenna Highly integrated with extremely low external part count
* * * *
Applications
* * * * Automotive remote keyless entry (RKE) Long range RF identification Remote fan and light control Garage door and gate openers
Ordering Information
Part Number Standard MICRF010BM Pb-Free MICRF010YM Operating Mode Fixed Shutdown Yes Package 8-pin SOIC
Typical Application
17cm 22AWG MAGNET WIRE
433.92Mhz 1000 bps Manchester Encoded On-Off Keyed Receiver
QwikRadio is a registered trademark of Micrel, Inc. The QwikRadio Ics were developed under a partnership agreement with AIT of Orlando, Florida.
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MICRF010
Pin Configuration
Standard 8-Pin SOIC (M)
Pin Description
Pin Number 1 2 3 4 Pin Name VSS ANT VDD CTH Pin Function Ground Return (input): ground return to the power supply. See "Applications Information" for bypass capacitor details. Antenna (Input): See "Applications Information" for information on input impedance. For optimal performance the antenna impedance should be matched to the antenna pin impedance. Power Supply (Input): Positive Supply input for the RF IC. Connect a low ESL, low ESR decoupling capacitor from this to VSS, with lead length kept as short as possible. [Data Slicing] Threshold Capacitor (External Component): Capacitor extracts the DC average value from the demodulated waveform, which becomes the reference for the internal data slicing comparator. See "Applications Information" for selection. Digital Output (Output): CMOS level compatible data output signal. Shutdown (Input): Shutdown-mode logic-level control input. Pull low to enable the receiver. This input is pulled-up internally to VDD. AGC Capacitor (External Component): Integrating capacitor for on-chip AGC (automatic gain control). See "Applications Information" for capacitor selection. Reference Oscillator (External Component or Input): Timing reference for on-chip tuning and alignment.
5 6 7 8
DO SHUT CAGC REFOSC
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Absolute Maximum Ratings(1)
Supply Voltage (VDDRF, VDDBB)................................... +7V Input/Output Voltage (VI/O) ................ VSS-0.3 to VDD+0.3 Max Input Power ................................................... +20dBm Junction Temperature (TJ) ..................................... +150C Storage Temperature Range (TS)........... -65C to +150C Lead Temperature (soldering, 10 sec.).................. +260C ESD Rating ............................................................. Note 3
Operating Ratings(2)
Supply Voltage (VDDRF, VDDBB) ...............+4.75V to +5.5V Max Input Power ....................................................... 0dBm RF Frequency Range ............................300MHz to 440Hz Data Duty-Cycle.............................................. 20% to 80% Reference Oscillator Input Range........... 0.2VPP to 1.5VPP Ambient Temperature (TA)........................ -40C to +85C
Electrical Characteristics(4)
4.75V VDD 5.5V, VSS = 0V; CAGC = 4.7F, CTH = 0.022F; fREFOSC = 9.794MHz (equivalent to fRF = 315MHz); data rate = 600 bps (Manchester encoded). TA = 25C, bold values indicate -40C TA +85C; current flow into device pins is positive, unless noted. Symbol IOP Parameter Operating Current Condition continuous operation, fRF = 315MHz Polled with 10:1 duty cycle, fRF = 315MHz Continuous operation, fRF = 433.92MHz Polled with 10:1 duty cycle, fRF = 433.92MHz ISTBY Standby Current Receiver Sensitivity(4) fIF fBW IF Center Frequency IF 3dB Bandwidth Spurious Reverse Isolation AGC Attack to Decay Ratio AGC Leakage Current Reference Oscillator ZREFOSC Reference Oscillator Input Impedance Reference Oscillator Source Demodulator ZCTH IZCTH(leak) CTH Source Impedance CTH Leakage Current Demodulator Filter Bandwidth Note 9 TA = +85C Note 5 150 100 2000 k nA Hz Note 7 Note 8 290 5.0 k A VSHUT = 0.8VDD fRF = 315MHz Note 4 fRF = 433.92MHz Note 4 Note 5 Note 5 ANT pin, RSC = 50 tATTACK / tDECAY TA = +85
(6)
Min
Typ 2.9 290 4.7 470 0.15 -105 -103 0.86 0.6 30 0.1 100
Max 4.5 7.5
Units mA A A A A dBm MHz MHz Vrms nA
0.5
RF Section, IF Section
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Symbol VIH VIL IOUT VOH VOL tR, tF
Notes:
Parameter Input High Voltage Input Low Voltage Output Current Output High Voltage Output Low Voltage Output Rise and Fall Time
Condition SHUT SHUT DO pin, push-pull DO pin, IOUT = -30A DO pin, IOUT = +30A DO pin, CLOAD = 15pF
Min 0.8
Typ
Max
Units VDD
Digital/Control Section 0.2 45 0.9 0.1 4 VDD A VDD VDD s
1. Exceeding absolute maximum ratings may damage the device. 2. The device is not guaranteed to function outside its operating ratings. 3. Devices are ESD sensitive, use appropriate ESD precautions. The device meets Class 1 ESD test requirements, (human body model HBM), in accordance with MIL-STD-883C, method 3015. Do not operate or store near strong electrostatic fields. 4. Sensitivity is defined as the average signal level measured at the input necessary to achieve 10-2 BER (bit error rate). The RF input is assumed to be matched to 50. 5. Parameter scales linearly with reference oscillator frequency fT. For any reference oscillator frequency other than 9.794MHz, compute new parameter value as the ratio:
fREFOSC MHZ x (parameter value at 9.79MHz ) 9.794MHz
6. Spurious reverse isolation represents the spurious components, which appear on the RF input pin (ANT) measured into 50 with an input RF matching network. 7. Series resistance of the resonator (ceramic resonator or crystal) should be minimized to the extent possible. In cases where the resonator series resistance is too great, the oscillator may oscillate at a diminished peak-to-peak level, or may fail to oscillate entirely. Micrel recommends that series resistances for ceramic resonators and crystals not exceed 50 and 100, respectively. 8. Crystal load capacitor is 10pF. See Figure 5 in "REFOSC" section for reference oscillator operation. 9. Parameter scales inversely with reference oscillator frequency fT. For any reference oscillator frequency other than 9.794MHz, compute new parameter value as the ratio:
9.794MHz x (parameter value at 9.794MHz) fREFOSCMHZ
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Typical Characteristics
Supply Current vs. Frequency
6.0 TA = 25 o C VDD = 5V CURRENT (mA) 4.5
4.0
Supply Current vs. Temperature
f = 315 MHZ VDD = 5V
CURRENT (mA)
3.5
3.0
3.0 Fix Mode, Continuous Operation 1.5 250 300 350 400 450 500
2.5 Fix Mode Continuous Operation 2.0 -40 -20 0 20 40 60 80 100
FREQUENCY (MHz)
TEMPERATURE ( o C)
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Functional Diagram
Figure 1. MICRF010 Block Diagram
Application Information and Function Description
"MICRF010 Block Diagram" above shows the IC partitioned into three sections: 1) UHF Downconverter, 2) OOK Demodulator, 3) Reference and Control. Also shown in the figure are two external capacitors (CTH, CAGC) and one timing element, which is usually a crystal. With the exception of a supply decoupling capacitor and antenna impedance matching network, these are the only external components needed by the MICRF010 to assemble a complete UHF receiver. For optimal performance it is highly recommended that the MICRF010 is impedance-matched to the antenna. The matching network will add an additional two or three components. The "SHUT" input is the only control input of the IC. It is used in polling operation for decreasing DC current consumption. This input is CMOS compatible and it is internally pulled-up. The IF Bandpass Filter Roll-off response of the IF Filter is 5th order, and the demodulator data filter has a 2nd order response. June 2005 6
Design Steps: The following steps are the basic design steps for using the MICRF010 receiver: 1. Select the reference oscillator 2. Select the demodulator filter bandwidth 3. Select the CTH capacitor 4. Select the CAGC capacitor
Step 1: Selecting The Reference Oscillator
All timing and tuning operations on the MICRF010 are derived from the internal Colpitts reference oscillator. Timing and tuning is controlled through the REFOSC pin in one of three ways: 1. Connect a crystal. 2. Drive this pin with an external timing signal. The specific reference frequency required is related to the system transmit frequency. Crystal Selection The smaller the crystal, the longer it takes for the oscillator to start from a shutdown operation. If shorter start-up time
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is desired, use crystals with lower ESR, which normally are bigger in size, like the HC49 package. "Application Hints 35" provides additional information and recommended sources for crystals. If using an externally applied signal, it should be AC-coupled and limited to the operating range of 0.2VPP to 1.5VPP. Selecting Reference Oscillator Frequency fT As with any super-heterodyne receiver, the difference between the internal LO (local oscillator) frequency fLO and the incoming transmit frequency fTX, should equal the IF center frequency. Equation 1 may be used to compute the appropriate fLO for a given fTX:
Slicing level time constant values vary somewhat with decoder type, data pattern, and data rate, but typically values range from 5ms to 50ms. This issue is covered in more detail in "Application Note 22." Optimization of the value of CTH is required to maximize range. Selecting Capacitor CTH The first step in the process is selection of a data-slicinglevel time constant. This selection is strongly dependent upon system issues including system decode response time and data code structure (that is, existence of data preamble, etc.) This issue is also covered in more detail in "Application Note 22." The effective resistance of RSC is listed in the electrical characteristics table as 150k at 315MHz, this value scales inversely with frequency. RSC value at other frequencies is given by equation (4), where fT is in MHz:
R SC = 150 9.7941 fT (4)
(1) Frequencies fTX and fLO are in MHz. Note that two values of fLO exist for any given fTX, distinguished as "high-side mixing" and "low-side mixing." High-side mixing results in an image frequency above the frequency of interest and low-side mixing results in a frequency below. There is generally no preference of one over the other. After choosing one of the two acceptable values of fLO, use Equation 2 to compute the reference oscillator frequency fT:
fT = 2 x fLO 64.5
f fLO = fTX 0.86 TX 315
CTH can be calculated using equation (5) with the knowledge of Rsc and .
C TH =
R SC
(5)
(2)
Recommended is 5x the bit-rate. A standard 20% X7R ceramic capacitor for CTH is generally sufficient. Refer to "Application Hint 42" for CTH and CAGC selection examples.
Frequency fT is in MHz. Connect a crystal of frequency fT to REFOSC on the MICRF010. Four-decimal-place accuracy on the frequency is generally adequate. The following table identifies fT for some common transmit frequencies.
Transmit Frequency (fTX) 315.0 MHz 390.0 MHz 418.0 MHz Reference Oscillator Frequency (fT) 9.7941 MHz 12.1260 MHz 12.9966 MHz
Step 3: Selecting CAGC Capacitor
The signal path has AGC (automatic gain control) to increase input dynamic range. The attack time constant of the AGC is set externally by the value of the CAGC capacitor connected to the CAGC pin of the device. To maximize system range, it is important to keep the AGC control voltage ripple low, preferably under 10mVPP once the control voltage attains its quiescent value. For this reason, capacitor values of at least 0.47F are recommended. The AGC control voltage is carefully managed on-chip to allow duty-cycle operation of the MICRF010. When the device is placed into shutdown mode (SHUT pin is pulled high), the AGC capacitor floats to retain the voltage. When operation is resumed, only the voltage drop, due to capacitor leakage, must be replenished. A relatively lowleakage capacitor such as a ceramic type is recommended
433.92 MHz 13.4916 MHz Table 1. Recommended Reference Oscillator Values For Typical Transmit Frequencies (high-side mixing)
Step 2: Selecting CTH Capacitor
Extraction of the DC value of the demodulated signal for purposes of logic-level data slicing is accomplished using the external threshold capacitor CTH and the on-chip switched capacitor "resistor" RSC, as shown in the block diagram.
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when the devices are used in duty-cycled operation. To further enhance duty-cycled operation, the AGC push and pull currents are boosted for approximately 10ms immediately after the device is taken out of shutdown. This compensates for AGC capacitor voltage drop and reduces the time to restore the correct AGC voltage. The current is boosted by a factor of 45.
(that is, the attack time constant is 10 times of the decay time constant). Generally the design value of 1:10 is adequate for the vast majority of applications. If adjustment is required, adding a resistor in parallel of the CAGC capacitor may vary the ratio. The value of the resistor must be determined on a case-by-case basis.
Selecting CAGC Capacitor in Continuous Mode A CAGC capacitor in the range of 0.47F to 4.7F is typically recommended. Caution! If the capacitor is too large, the AGC may react too slowly to incoming signals. AGC settling time, from a completely discharged (zero-volt) state is given approximately by Equation 6: t = 1.333 x CAGC - 0.44 (6)
where: CAGC is in F, and t is in seconds.
Selecting CAGC Capacitor in Duty-Cycle Mode Voltage droop across the CAGC capacitor during shutdown should be replenished as quickly as possible after the IC is enabled. As mentioned above, the MICRF010 boosts the push-pull current by a factor of 45 immediately after startup. This fixed time period is based on the reference oscillator frequency fT. The time is 10.9ms for fT = 12.00MHz, and varies inversely with fT. The value of CAGC capacitor and the duration of the shutdown time period should be selected such that the droop can be replenished within this 10ms period. Polarity of the droop is unknown, meaning the AGC voltage could droop up or down. The worst-case from a recovery standpoint is downward droop, since the AGC pull-up current is 1/10th magnitude of the pull-down current. The downward droop is replenished according to the Equation 7:
I CAGC = V t
(7)
where: I = AGC pull-up current for the initial 10ms (67.5A) CAGC = AGC capacitor value t = drop recovery time V = drop voltage For example, if user desires t = 10ms and chooses a 4.7F CAGC, the allowable droop is about 144mV. Using the same equation with 200nA, the worst-case pin leakage, and assuming 1A of capacitor leakage in the same direction, the maximum allowable t (shutdown time) is about 0.56s for droop recovery in 10ms. The ratio of decay-to-attack time-constant is fixed at 1:10 June 2005 8
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The Demodulator Filter Bandwidth
There is no external control to set the demodulator bandwidth. The maximum bandwidth is 2000 hertz at 315 MHz. Maximum bandwidth scales linearly with operating frequency. To minimize data pulse stretching, one must calculate the "demodulator BW required" to be certain that it does not exceed demodulator filter bandwidth of MICRF010 at operating frequency. For "demodulator BW required" calculation, one needs to identify the shortest pulse within the data profile and use equation 8 below:
protection diodes at all input and output pins are not shown.
CTH Pin
VDD PHI2B PHI1B
Demodulator Signal
TG2
TG1
~1.6V
CTH
VSS
PHI2
VSS
PHI1
Demodulator BW Required =
0.65 (8) shortest pulse - width
Figure 2. CTH Pin
Refer to the "Electrical Characteristics" for the exact filter bandwidth at a chosen frequency.
Power Supply Bypass Capacitors Supply bypass capacitors are strongly recommended. One example is to use 0.1uF ceramic capacitor in parallel with 100pF ceramic capacitor for VDD. Data Squelching During quiet periods (no signal), the data output (DO pin) transitions randomly with noise. Most decoders can discriminate between this random noise and actual data. For some systems, random transition due to noise during quiet period is a problem. There are three possible approaches to reduce this output noise: 1. Analog squelch to raise the demodulator threshold. 2. Digital squelch to disable the output when data is not present. 3. Output filter to filter the (high frequency) noise glitches on the data output pin. The simplest solution is to perform analog squelch by inducing a small offset, or squelch voltage, on the CTH pin so that noise does not trigger the internal comparator, Usually 20mV to 30mV on CTH pin is sufficient. This may be achieved by connecting a several-meg-ohm resistor from the CTH pin to either VSSBB or VDDBB, depending upon the desired offset polarity. Since MICRF010's receiver AGC noise at the internal comparator input is always the same (set by the AGC), the squelch-offset requirement does not change as the local noise strength changes from installation to installation. Introducing squelch will reduce sensitivity and range. One should introduce minimal offset to sufficiently quiet the output. Typical squelch resistor values range from 10M to 6.8M for low to high squelch strength.
Figure 2 illustrates the CTH pin interface circuit. The CTH pin is driven from a N-Channel MOSFET source-follower with approximately 10A of bias. Internal control signals PHI1/PHI2 are related in a manner such that the impedance across the transmission gates looks like a "resistance" of approximately 150k. The DC potential at the CTH pin is approximately 1.6V
CAGC Pin
VDD
7uA Comparator
16uA
CAGC
Timeout 85uA 160uA
VSS
Figure 3. CAGC Pin
I/O Pin Interface Circuitry
Interface circuitry for the various I/O pins of the MICRF010 are diagrammed in Figures 2 through 8. The ESD June 2005 9
Figure 3 illustrates the CAGC pin interface circuit. The AGC control voltage is developed as an integrated current into a capacitor CAGC. The attack current is nominally 1.5A, while the decay current is a 10 times scaling of this, approximately 15A. Signal gain of the RF/IF strip inside the IC diminishes as the voltage on CAGC decreases. By simply adding a capacitor to CAGC pin, the attack/decay time constant ratio is fixed at 10:1. Modification of the attack/decay ratio is possible by adding resistance from the CAGC pin to either VDDBB or VSSBB, as desired. Both the push and pull current sources are disabled during shutdown, which maintains the voltage across CAGC, and improves recovery time in duty-cycled applications. To further improve duty-cycle recovery, both push and pull currents are increased by 45 times for approximately 10ms after release of the SHUT pin. This allows rapid recovery of any voltage droop on CAGC while in shutdown.
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DO Pin The output stage for the digital output (DO) is shown in Figure 4. The output is a 45A push and 45A pull switched-current stage. This output stage is capable of driving CMOS loads. An external buffer-driver is recommended for driving high capacitance loads.
VDD
SHUT Pin
VDD Q1 VSS SHUT Q3 VSS
Figure 6. SHUT Pin
Q2 to Interna Circuits
45uA Comparator
DO
45uA
VSS
Figure 4. DO Pin
REFOSC Pin The REFOSC input circuit is shown in Figure 5. Input impedance is quite high (290k). This is a Colpitts oscillator, with internal 10pF capacitors.
Externally applied signals should be AC-coupled, amplitude limited to approximately 0.5VPP. The nominal DC bias voltage on this pin is 1.4V
Active Bias REFOSC 10pF 10pF VSS 200k 250 30uA VSS VDD
Control input circuitry is shown in Figure 6. The standard input is a logic inverter constructed with minimum geometry MOSFETs (Q2, Q3). P-Channel MOSFET Q1 is a large channel length device, which functions essentially as a "weak" pull-up to VDDBB. Typical pull-up current is 5A, leading to an impedance to the VDD supply of typically 1M.
Figure 5. REFOSC Pin
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Additional Applications Information
In addition to the basic operation of the MICRF010, the following enhancements can be made. In particular, it is strongly recommended that the antenna impedance is matched to the input of the IC.
Frequency (Mhz) 300 305 310 315 320 325 330 335 340 345 350 355 360 365 370 375 380 385 390 395 400 405 410 415 420
S11 Mag, angle 0.944,-36.65 0.940,-37.499 0.942,-37.579 0.945, -37.66 0.943,-38.237 0.942, -38.814 0.94, -39.39 0.938, -39.967 0.937, -40.544 0.935, -41.12 0.933, -41.697 0.931, -42.274 0.93, 42.85 0.928, -43.427 0.926, -44.004 0.925, -44.581 0.923, -45.157 0.921, -45.734 0.92, -46.311 0.917, -46.729 0.914, -47.148 0.912, -47.566 0.909, -47.985 0.907, -48.403 0.906, -48.797 0.909, -49.152 0.911, -49.507 0.911, -49.925 0.904, -50.571
Z11, ohms 14.45-j150 14.84-j145 14.28-j145 13.48-j145 13.58-j143 13.43-j140 13.5-j138 13.59-j136 13.44-j134 13.51-j132 13.57-j130 13.62-j123 13.48-j126 13.52-j124 13.57-j122 13.42-j120 13.46-j118 13.49-j117 13.35-j115 13.6-j114 13.89-j113 14.00-j112 14.25-j110 14.34-j109 14.28-j108 13.63-j107 13.15-j107 12.94-j106 13.66-j104
C3, pF 2.2 2.2 2.2 2.2 2 1.8 1.8 1.8 1.8 1.8 2 2.2 2.2 2 1.8 2.2 2 1.8 1.8 1.8 2 1.8 1.8 2.2 2 2 1.8 1.8 1.8
L2, nH 47 47 47 47 47 47 47 43 43 43 39 36 36 36 36 33 33 33 33 33 30 30 30 27 27 27 27 27 27
Antenna Impedance Matching
Figure 7. Antenna Pin Input Impedance
Figure 7 and Table 2 presents the antenna pin input impedance. The Antenna pin can be matched to 50 with a high pass circuit as shown in Figure 8. That is, a shunt inductor from the ANT Pin to ground and a series capacitor from ANT Pin to the antenna.
C3 ANT Pin L2
425 430 435 440
Table 2 Figure 8. Antenna with Matching Network to ANT Pin
Inductor values may be different from Table 2, depending on PCB material, PCB thickness, ground configuration, and how long the traces are in the layout. Values shown were characterized for a 0.031 inch thickness, FR4 board, solid ground plane on bottom layer, and very short traces. MuRata and Coilcraft wire-wound 0603 or 0805 surface mount inductors were tested, however, any wire-wound inductor with high SRF (self-resonance frequency) should do the job.
Shutdown Function Duty-cycled operation of the MICRF010 (often referred to as polling) is achieved by turning the MICRF010 on and off via the SHUT pin. The shutdown function is controlled by a logic state applied to the SHUT pin. When VSHUT is high, the device goes into low-power standby mode. This pin is pulled high internally, and it must be externally pulled low to enable the receiver.
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Application Example: 433.92Mhz, 1000 bps Manchester Encoded On-Off Keyed Receiver
17cm 22 AWG MAGNET WIRE
Bill of Materials
Item 2 4 1 5 6 7 3 8 9 11 12 13 14 15 16 17 18 Qty Reference 1 1 1 1 1 1 2 1 1 1 1 3 1 1 2 1 1 C3 C7 C2 C8B C8 C9 C5,C10 J2 J1 L3 L5 L6,L7,L9 L8 R4 R5, R6 U1 Y1 Value 5.6pF 100pF 4.7pF NL 0.47uF 100nF 4.7uF Description CAPACITORS 5.6pF Capacitor, 0603, 50VDC, 5% 100pF Capacitor, 0603, 50VDC, 5% 4.7pF Capacitor, 0603, 50VDC, 5% Manufacturer MuRata MuRata MuRata MuRata MuRata MuRata Part# GRM1885C1H5R6DZ01B GRM1885C1H101JA01B GRM1885C1H4R7CZ01B GRM188R61A474KA61B GRM188R71E104KA01B GRM21BF51A475ZA01B
0.47uF Capacitor, 0603, 25VDC, 10% 100nF Capacitor, 0603, 25VDC, 10% 4.7uF Capacitor, 0805, 10VDC, +80-20% CONNECTORS 4 Pin Header 4 Pin Header ANTENNA 17cm 22 AWG magnet wire INDUCTORS 30nH 30nH Inductor, 0603, 5% 24nH 24nH Inductor, 0603, 5% ZCB-0603 Ferrite bead, >600 Ohm @ 100MHz UL Ferrite bead, >600 Ohm @ 100MHz RESISTORS 100K UL SEMICONDUCTORS MICRF010BM 300-440MHz UHF Receiver 13.4916MHz 10pF, no built-in capacitor
Major League Electronics TSHS-148-S-06-A-GT Consolidated Coilcraft Coilcraft ACT ACT VISHAY 0603CS-30NXJB 0603CS-24NXJB ZCB-0603 ZCB-0603 CRCW06031003F
MICREL Abracon
MICRF010BM ABl-13.4916MHz-10
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PCB Layout Information
The MICRF010 evaluation board was designed and characterized using two sided 31 mils thick FR4 material with 1 ounce copper clad. If another type of printed circuit board material were to be substituted, impedance matching and characterization data stated in this document may not be valid. The gerber files for this board can be downloaded from the Micrel website at www.micrel.com. All Units for PCB shown are in mils.
PCB Silk Screen
PCB Component Side Layout
PCB Solder Side Layout
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Package Information
0.026 (0.65) MAX) PIN 1
0.157 (3.99) 0.150 (3.81)
DIMENSIONS: INCHES (MM)
0.050 (1.27) TYP
0.020 (0.51) 0.013 (0.33) 0.0098 (0.249) 0.0040 (0.102) 0-8 SEATING PLANE 45 0.010 (0.25) 0.007 (0.18)
0.064 (1.63) 0.045 (1.14)
0.197 (5.0) 0.189 (4.8)
0.050 (1.27) 0.016 (0.40) 0.244 (6.20) 0.228 (5.79)
8-Lead SOIC (M)
MICREL, INC. 2180 Fortune DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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